Questa One offers faster engines, enables engineers to work more nimbly, and requires less workload to support larger and more complex designs, from IP to systems-on-a-chip (SoC) and systems, and has been developed with consideration for advanced 3D integrated circuits, chiplet-based designs, and software-defined architectures.
“Questa One transforms the integrated circuit design process to address the productivity gap in verification and solves the growing challenges the integrated circuit industry faces with increasingly complex designs,” said Abhi Kolpekwar, vice president and general manager of Digital Verification Technologies at Siemens Digital Industries Software. “Questa One leverages new technical advancements to deliver the fastest functional, fault, and formal verification engines on the market, but customers tell us that performance alone isn’t enough: they also need deeper connectivity between our unparalleled verification, validation, and testing workflows, which is precisely what Questa One delivers. Combined with our application of AI, Siemens verification solutions are providing significant productivity gains for early adopters in the areas of smart creation, smart regression, smart analysis, smart engines, and smart debugging.”.
The Questa One smart verification solution includes multiple technical advancements, including:
Questa One Coverage Acceleration software has achieved coverage targets 50 times faster than traditional testbench solvers, combining higher and faster coverage results with the advantages of Universal Verification Methodology (UVM) constrained random proof generation.
Questa One DFT Simulation Acceleration software has achieved 8x faster gate-level design for testing (DFT) for serial pattern simulations by leveraging Questa One Parallel Simulation software and is tightly integrated with the industry-leading Tessent™ Streaming Scan Network (SSN) architecture.
Questa One Fault Simulation Acceleration software has delivered 48 times faster performance and supports DFT and functional safety fault simulation applications. It is the only software that supports the User-Defined Fault Modeling (UDFM) feature in Tessent.
Questa One Stimulus Free Verification software empowers engineers to achieve new levels of productivity. Its unique approach, which combines engines and unifies applications, has proven to reduce total processing times from over 24 hours to less than 1 minute for complex, open-source, SoC-level reference designs. The integration of 20 different stimulus-free analyses, AI, and automation delivers innovative solutions, such as self-correcting linting and AI-powered generative SVA property creation and verification.
The Questa One Avery Verification IP software is based on Avery's high-quality VIP and high-coverage conformance test suites (CTS). Protocol-aware debugging and protocol-aware coverage analysis help increase productivity, and the accelerated VIP allows the same CTS, test suite, and stimulus from Questa One Sim to be reused in Veloce CS emulation and prototyping systems.
Availability:
The Questa One intelligent verification solution will be available in June 2025. To learn more about how Siemens is enabling the semiconductor and electronics systems industry to commercialize the world’s most advanced 3D integrated circuits, chiplet-based designs, and software-defined systems, click here.
