In combination with Siemens' Tessent DefectSim technology, the new Tessent AnalogTest software helps reduce the coding time for analog circuit testing on integrated circuits (ICs) by automatically generating low-impact design-to-test (DFT) circuits and digital test patterns for virtually any analog circuit block. Tests run in less than one millisecond on almost any tester, and defect coverage can be verified in simulation up to 1,000 times faster than specification-based testing.
The introduction of Tessent AnalogTest marks the first automated DFT solution for analog circuits on integrated circuits, providing digital vectors to efficiently test and calculate test coverage before moving to silicon production. The solution leverages digital automated test equipment (ATE) for analog circuit development, reducing costs and improving productivity compared to using more expensive mixed-signal testers. This acceleration allows integrated circuit designers to achieve and verify high defect coverage (>90%) based on IEEE P2427 in a matter of hours for individual circuit blocks, setting new speed standards and dramatically reducing time to market.
The software uniquely expands its structural test generation capabilities by producing simulation test benches from specification-based tests, utilizing the intuitive, high-level ICL and PDL test descriptions specified by IEEE P1687.2, the analog extension of the widely used digital IJTAG standard. These tests can verify analog test flow and defect coverage for algorithmic trimming, parametric reloading tests, or ISO 26262 functional safety metrics. Furthermore, incorporating scan tests can further enhance these metrics.
