Modern printed circuit boards (PCBs) are increasing in component density, and accessing pins in certain packages, such as BGA and LGA, is practically impossible. This poses the greatest challenge for any test tool based on physical contact with pins or nodes.
Because boundary scan was designed to be the practical solution to this challenge, it has become a vital tool for achieving the correct boundary scan chain from the design stage. XJTAG DFT Assistant for Altium Designer helps validate the correct connectivity in the boundary scan chain through full integration with Altium Designer.
“The XJTAG DFT Assistant for Altium Designer provides technicians with a free, easy-to-use extension to check whether boundary scan chains are correctly connected and terminated at the schematic capture stage, well before PCB production.
By detecting and correcting these faults in time, companies save time and money,” says Simon Payne, CEO of XJTAG.
“While the first prototype is being manufactured, XJTAG DFT Assistant allows a preliminary project to be exported from Altium Designer to XJTAG's development software where additional tests can be developed. These can then be used as real hardware tests as soon as they are available. This provides a vital new capability to electronics engineers worldwide.”
The XJTAG DFT Assistant for Altium Designer comprises two key elements: the XJTAG Chain Checker and the XJTAG Access Viewer.
The XJTAG Chain Checker detects and identifies common errors in a JTAG chain scan, such as incorrectly connected Test Access Ports (TAPs). A simple connection error will prevent the entire chain from being scanned. The XJTAG Chain Checker identifies connection errors and reports them to the developer during the design process. Incorrectly configured TAPs are also detected.
The XJTAG Access Viewer highlights the amount of schematic accessible via boundary scan, allowing the user to immediately see which components are accessible using boundary scan and where test coverage can be extended.
“We are delighted that XJTAG is introducing this extension, and we believe our customers will find it extremely beneficial in their product development,” commented Daniel Fernsebner, Corporate Director, Technology Partnerships and Business Development, Altium.
As a specialist in boundary scan technology, XJTAG has valuable experience in resolving PCB-related issues, enabling it to prevent a boundary scan chain from functioning correctly. By applying this knowledge to the XJTAG DFT Assistant for Altium Designer during the schematic capture stage, engineers can benefit from this expertise in our development environment and prior to hardware production.
Boundary scan, defined by the IE3 as a family of standards (IEEE 1149.x and adopted by all major semiconductor manufacturers), provides electrical access to all compatible integrated components on a PCB using a boundary scan chain—a simple 4- or 5-signal bus that sequentially connects compatible JTAG components. Through boundary scan, access can be extended to include compatible non-JTAG components for connectivity and functional testing, as well as for programming non-volatile memories and FPGAs/CPLDs.
Usable from prototypes to production testing, boundary scan allows for the detection of a wide range of faults. Detected faults include short circuits, open circuits, high and low tap faults, and pull-up/down resistor faults. XJTAG systems also allow you to locate faults in specific networks without needing physical access to pins or expensive tools like in-circuit testers, flying probes, or spike beds.
XJTAG DFT Assistant for Altium Designer is a free extension that can be downloaded from the Extensions panel.
