CHERI represents a transformative hardware security architecture designed to mitigate memory security vulnerabilities, a major source of modern cyberattacks, and provides granular compartmentalization to enhance software robustness and resilience.
EnSilica will utilize Codasip’s portfolio of 32- and 64-bit CHERI RISC-V processors as the foundation for developing customer-specific System-on-Chip (SoC) integrated circuits. These secure platforms will integrate processing, PQC and classic encryption hardware, and custom analog and digital functionalities to meet the precise requirements of the end application.

Ian Lankshear, CEO of EnSilica, stated: “Cybersecurity has become a defining challenge for automotive, industrial, and defense systems, with increasingly sophisticated and larger-scale attacks. This partnership positions EnSilica at the forefront of delivering cyber-resistant chips that combine the security of CHERI’s hardware-strengthened memory with post-quantum cryptography. By building on Codasip’s advanced CHERI RISC-V processors, we can offer customers complete, application-specific ASIC solutions with security and functional reliability engineered from the ground up. We are excited to be working with Codasip to bring this new generation of trusted silicon to market.”

Dr. Ron Black, CEO of Codasip, added: “This partnership will help unlock the full potential of our next-generation 32-bit and 64-bit CHERI RISC-V CPUs. Developed in accordance with the ISO 26262 functional security and ISO 21434 cybersecurity standards, our processors come with a complete ecosystem that includes the CHERI toolchain, CHERI Linux, and CHERI RTOS. By combining this with EnSilica’s expertise in ASICs, we can accelerate the adoption of CHERI-based security in mission-critical applications.”