Microchip Technology Inc. today announced the expansion of its data center solutions portfolio and its entry into the memory infrastructure market with the first commercially available serial memory controller. The SMC 1000 8x25G enables compute-intensive CPUs and other systems-on-a-chip (SoCs) to quadruple the number of parallel-connected DDR4 DRAM memory channels within the same package size. Microchip's serial memory controllers provide these compute-intensive platforms with increased memory bandwidth and medium independence with extremely low latency.
The increase in the number of processing cores in CPUs has led to a decrease in the average memory bandwidth available per core, as CPUs and SoCs can no longer accommodate the number of parallel DDR interfaces on a single chip required to meet the needs of the increased number of cores. The SMC 1000 8x25G connects to the CPU via the 25 Gbps lanes of the OMI (Open Memory Interface) and to the memory via a 72-bit DDR4 3200 interface. This results in a significant reduction in the number of pins required on the main CPU or SoC per DDR4 memory channel, thus enabling more channels and greater available memory bandwidth.
An OMI-compliant CPU or SoC can utilize numerous media types with varying cost, power, and performance levels without requiring a separate memory controller for each type. In contrast, current CPU and SoC memory interfaces are typically tied to specific DDR interface protocols, such as DDR4, and their corresponding interface speeds. The SMC 1000 8x25G is Microchip's first media-independent memory infrastructure product in its portfolio for the OMI interface.
Data center applications demand OMI-based DDIMM memory products that deliver the same high-performance bandwidth and low latency as current parallel DDR-based memory products. Microchip's SMC 1000 8x25G incorporates an innovative low-latency design that increases latency to less than 4 ns for first DRAM data access while maintaining the same access performance for subsequent data. As a result, OMI-based DIMM products offer virtually the same bandwidth and latency levels as comparable LRDIMM products.
“At Microchip, we are excited to introduce the first serial memory controller device on the market,” said Pete Hazen, vice president of Microchip’s Data Center Solutions business unit. “New memory interface technologies, such as OMI (Open Memory Interface), enable a wide range of SoC applications to meet the growing memory requirements of high-performance data center applications. Microchip’s entry into the memory infrastructure market underscores our commitment to improving performance and efficiency in data centers.”.
“IBM customers’ workloads demand more intensive use of memory, which is why we made the strategic decision to have the POWER processor’s memory interfaces use OMI standard interfaces to increase memory bandwidth,” said Steve Fields, chief architect of IBM Power Systems. “IBM values the agreement with Microchip for the supply of this solution.”.
SMART Modular, Micron, and Samsung Electronics are developing several efficient 84-pin DDIMMs (DDR4 Differential Dual-Inline Memory Modules) with capacities ranging from 16 GB to 256 GB. These DDIMMs will leverage the SMC 1000 8x25G and will seamlessly connect to any 25 Gbps interface compliant with OMI.
“The OMI (Open Memory Interface) standard provides an efficient pinout serial memory interface so that a growing number of CPU and SoC applications can deliver the memory bandwidth and seamless transition between a growing number of media types, such as storage memory,” said Myron Slota, president of the OpenCAPI Consortium. “The OpenCAPI Consortium provides royalty-free intellectual property (IP) for both master and target units, and drives numerous initiatives that ensure standards compliance.”
“Google customers rely on data-intensive applications, such as machine learning and data analytics, which demand high-performance memory,” said Rob Sprinkle, technical lead for platform infrastructure at Google LLC. “Google strongly supports open standards-based initiatives like OMI (Open Memory Interface), which provides a high-performance memory interface to meet these important bandwidth and latency targets.”.
Development Tools:
The SMC 100 is supplied with ChipLink design and diagnostic tools to support customers developing IMO-compliant systems. These tools provide powerful debugging, diagnostic, configuration, and analysis capabilities with an easy-to-use interface.
