The new specification gives designers freedom regarding SerDes signaling over PCIe for Gigabit Ethernet, as well as full USB-C compatibility, offering USB 3.2 Gen1 and DisplayPort Alt Mode over a single USB interface. This new version is further evidence of SGET's ongoing efforts to future-proof the SMARC Computer-on-Module (COM) standard—including the benefit of implementing the latest technologies with full backward compatibility.

The new SMARC 2.1.1 design guide is a significant contribution to standardizing the fragmented and proprietary COM market for Arm-based processor technologies.
Nearly 95% of Arm-based COMs are not standardized, as they mostly feature silicon-specific pinouts. The pinouts of these modules are poorly defined and documented, highly proprietary, lack peer review, and are constantly changing. This makes it nearly impossible for potential users to find a suitable long-term path through this complex landscape, not to mention the inability to reuse or upgrade their designs with next-generation silicon, which significantly impacts OEMs' return on investment. Therefore, customers will welcome the SMARC 2.1.1 module specification and its associated 2.1.1 Design Guide as one of the best-defined, most detailed, silicon-independent, and future-proof open specifications on the market. “Furthermore, x86 designs will benefit from this well-defined and designed standard,” says Markus Mahl, a contributor to the new version.

New features in the design guide:
The SMARC 2.1.1 design guide includes a new chapter on SerDes implementations and offers more examples of full-featured USB-C implementations, including DisplayPort Alt mode, as well as updated and expanded options for display interfaces. In addition, the chapter on module power has been optimized to provide better explanations of the power-up process and the four separate power domains. New chapters have been added on how to implement the RESET_OUT signal and to demonstrate the increased influence of track stubs across high-speed signals, and track loss simulations have been added. New considerations regarding SPI and eSPI topology complete the enhancements.

Download the Guide