Applying the optimized process across various applications will allow Toshiba to expand its product line in areas such as microcontrollers, wireless communication ICs, motor controllers, and power supply ICs.
The IoT market is seeing strong demand for low-power devices in areas including wearables and medical devices. In response, Toshiba has adopted the third generation of Silicon Storage Technology's SuperFlash® cell technology, combined with its own 65nm logic process technology. The company has also refined circuitry and manufacturing processes in developing an ultra-low-power logic process with embedded flash. Microcontrollers for industrial and consumer applications that utilize this process can reduce power consumption by approximately 60% compared to current technology.

Following its first series of microcontrollers, Toshiba plans to launch samples of BLE (Low Energy Bluetooth) products, the short-range wireless technology, in fiscal year 2016. The company also plans to apply the 65nm process to its family of wireless communication integrated circuits that can optimize the use of low-power features, including NFC (Near Field Communication) controllers and contactless cards.

In addition to the advantages of low power consumption, the process technology contributes to shorter development times, as application software can be easily written and rewritten to flash memory during development. Through engineering advancements in ultra-low power devices, and by promoting further development of specialized flash peripheral circuit technology and analog logic and circuit technology, Toshiba will continue to meet the growing demand for low-power applications. The company aims to reduce power consumption for entire systems, targeting 50μA/MHz operation, and is developing innovative IoT products. In applications where significant cost reductions are involved, Toshiba has developed an integrated NVM process that adopts Yield Microelectronics Corporation's MTP (Multi-time Programmable) single-poly cells on Toshiba's 130nm logic process technology.
The NVM and analog circuits are integrated onto a single chip that can incorporate multiple functions conventionally performed by a multi-chip system. This reduces the number of pins and results in smaller packages. Applying MTP specifications for write times improves the performance of the new process while limiting the number of mask pattern lithography steps to three or fewer, or even none. By using MTP to fine-tune output accuracy, Toshiba will expand its product line in fields where higher precision is essential, such as power management integrated circuits.
For more information or a quote, please contact