Renesas applied its proprietary 65-nanometer (nm) silicon processor in the thin box (SOTB, Note 1) for the development of embedded SRAM prototypes. The prototype SRAM simultaneously achieves both a high-speed read time of 1.8 ns during active operation and an ultra-low power consumption of 13.7 nW/Mbit in standby mode. The SRAM achieves the lowest standby power consumption characteristics (Note 2) in the industry, which is only one-thousandth of the standby power consumption, by utilizing dynamic substrate back-bias control, taking advantage of the SOTB structure.
Recently, in the rapidly growing IoT market, all applications will be wirelessly connected, and therefore there is a strong desire for battery-free operation, which utilizes natural energy sources such as light, vibration, or heat and consumes less power for longer battery life. Furthermore, when longer battery life is achieved, battery replacement will no longer be necessary, making applications maintenance-free.
At the same time, achieving miniaturization of end products is essential for the development of IoT applications. Reducing the power consumption of ASSPs by at least an order of magnitude would enable miniaturization, as it reduces the capacity of the currently used battery. As an effort to reduce power consumption in ASSPs for IoT, one technique involves operating the application intermittently, typically in standby mode and only switching to active mode when data processing is required. Specifically, the most common procedure for reducing power consumption in standby mode is to cut power to the circuit after saving the necessary data, either to an external device or to internal non-volatile memory. While this method is effective when standby times are relatively long, in systems that frequently switch between active and standby modes, saving data to non-volatile memory and the subsequent reset operation becomes a significant overhead. There are even cases where, conversely, this actually increases power consumption.
The new technology employs a method that reduces the power consumption of the built-in SRAM in standby mode. This allows intermittent operation to occur frequently without increasing power consumption, thus eliminating the need to store data in non-volatile memory and leading to improved power efficiency.
Renesas' previous efforts in embedded SRAM include a prototype embedded SRAM with a 28 nm HKMG (high-k metal gate) structure and a high-performance embedded SRAM with a 16 nm FinFET (Fin field-effect transistor) structure, both of which utilize cutting-edge process technologies. These embedded SRAM technologies have been adopted in Renesas' R-Car automotive infotainment system (SoCs). Renesas developed a circuit technology that dynamically controls substrate bias using SOTB process technology, enabling the quiescent leakage current to be reduced to approximately one-thousandth of the power compared to normal standby mode.
Key features of the new SRAM technology incorporated:
1) It achieves the industry's lowest standby power of 13.7 nW/Mbit, as well as a high-speed read operation of 1.84 ns by using substrate bias control that leverages the SOTB structure
Recently, the miniaturization of semiconductor processes and the challenge of voltage scaling are causing problems, such as increased leakage current due to the low threshold voltage of semiconductor device elements and deterioration of the lower operating voltage limit due to increasing variations in device elements. These problems result in higher standby power consumption and higher operating power consumption due to the inability to reduce operating voltages, making it difficult to decrease power consumption.
To address this problem, Renesas adopted its internally developed SOTB process technology, which efficiently suppresses variations between device elements and improves the turn-on/turn-off current ratio, and has prototyped an embedded SRAM using this new technology. SOTB process technology differs from the planar transistor structure formed on the silicon substrate in previous process technologies, as an oxide film (buried oxide) is buried beneath a thin layer of silicon on the wafer substrate. This technology enables dopant-free channel transistors that do not require doping of the thin-film silicon layer. By creating a dopant-free channel structure, variations in the transistor's threshold characteristics can be reduced to approximately one-third of those of the previous planar-type overall structure transistor. This reduction in variations has a similar effect to the FinFET structure adopted in the latest generation of SoCs. Reducing transistor performance variations achieves stable operation at low voltages around 0.5 V. Furthermore, the adoption of a thin BOX layer in the SOTB process technology allows for significant changes in the transistors' threshold value characteristics by controlling the silicon substrate potential beneath the BOX. This is a feature that could not be achieved with the previous planar bulk structure or the FinFET structure. Leveraging this feature, Renesas provides an integrated regulator that can dynamically control the substrate bias of the built-in SRAM, allowing the selection of one of three operating modes (normal mode, low-power mode, and high-speed mode) or standby mode, depending on the applied substrate bias.
Using this regulator, Renesas confirmed that when high-load computational processing is required, switching from normal mode to high-speed mode—that is, setting the substrate potential from zero bias to a forward bias—changes the read access time from 4.58 ns to 1.84 ns, thus achieving a 2.5-fold increase in speed compared to normal mode. Conversely, in standby mode, applying reverse bias to the substrate potential reduces leakage current by three orders of magnitude to 13.7 nW/Mbit, which is only one-thousandth of the power consumption during standby. Leakage power in normal mode.
2) When the substrate bias and signal are dynamically controlled in response to the computational load, both high-speed operation and low power consumption can be achieved depending on the operating mode. Stable operation must be ensured under all bias conditions. Even if variations in embedded SRAM characteristics are reduced by adopting the SOTB structure compared to previous planar global structure devices, these variations cannot be eliminated entirely. Therefore, it becomes important to ensure design margins so that the memory cell with the largest variation can function. In ASSPs for IoT applications, there are many cases where several SRAM macros are placed around the chip. The design margin required for each individual SRAM macro unit will vary according to the probability that the memory cell with the largest variation is included in the macro. Typically, the same worst-case design margins were assigned to each macro so that worst-case operation could be reliably guaranteed for all macros on the chip. However, this meant that there were always macros for which the margins were excessive.
To improve this situation, Renesas proposed a replication circuit method in which the read pulse width could be fine-grainedly optimized (Note 3) to eliminate excessive design margins. This makes it possible to reduce active power by up to 20% during read operations.
The low-power embedded SRAM achieves both low standby power consumption and increased operating speed, which were difficult to achieve with the continuous progress of semiconductor process miniaturization. By enabling ASSPs to adopt embedded SRAM with the SOTB structure, Renesas plans to support energy harvesting operations and contribute to the development of maintenance-free IoT applications that do not require battery replacement. Furthermore, by including embedded SRAM in low-power ASSPs manufactured using the 65nm SOTB process, Renesas plans to contribute even more to building a smarter society.
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Note 1: BOX: buried rust
Note 2: As of June 8, 2017, according to Renesas research
Note 3: In small macro units
