Introduction:
Contemporary processor-based designs used in the embedded systems industry require power to be supplied at different voltages. In addition to having different values, the voltage rails must follow a specific sequence upon startup: the processor core, related peripherals, I/O buses (such as LVDS, I2C, SPI, etc.), and memory resources. This sequencing prevents the risk of high inrush currents that could damage sensitive subsystem components during the startup process.

The trend toward increased levels of integration has meant that more of the functionality of an embedded system is typically included in a single System-on-a-Chip (SoC) to reduce board footprint and bill of materials (BoM) costs. Such SoCs require multiple power rails, each with the appropriate voltage level, to supply power to their associated pins. Those not focused on SoC architectures will typically use programmable logic, and when FPGAs reach a significant size, engineers will face similar (and in some cases, greater) power rail complexity. This approach sometimes needs to be extended to other on-board components, such as discrete devices (MOSFETs, IGBTs, etc.), sensors (CMOS imaging devices, magnetometers, etc.), or actuators (motor drivers, LED drivers, etc.), which may require dedicated power lines.

Even a relatively simple integrated system implementation can contain a significant number of rails (it is not uncommon for the number to exceed 10). Engineering measures must be taken to ensure the correct sequence is maintained: the output supplied by one power regulator must reach a sufficient level before the regulators for other voltage lines are activated. Since timing is easier to measure accurately than voltage, a time-based approach is often more effective, as it relies on the expectation that the desired value on a voltage rail will be reached within a predetermined timeframe.

Although the time between the activation of each rail is usually very short (a matter of milliseconds), it can sometimes be longer (several seconds, in fact). If, for example, an electromechanical component of the system, such as a heater, needs to reach its optimal temperature before the subsequent system elements are activated, or if the central processing unit needs to complete a calibration procedure, the required time increases, and the design engineer must be aware of this.

If the discrete power converters integrated into the system have the correct trigger pins and power outputs, engineers can use the correct power signal to ensure that the next converter in the sequence will only turn on when the preceding rail has reached a value sufficient to trigger that signal. If one or more converters lack a trigger input, engineers can achieve sequencing by using the turn-on signal to drive the gate of a MOSFET connected in series with the output.

In cases where a reliable power supply signal is unavailable, engineers may require additional circuitry to provide assistance. This circuitry allows the output voltage of one power converter to be sampled to generate a trigger signal for another power converter. One alternative to voltage sampling is the use of timing circuitry. However, either approach requires a significant number of components, resulting in an expensive bill of materials, a large footprint on the printed circuit board, and the allocation of additional engineering resources. Furthermore, discrete arrangements often define a reverse sequence when the system is powered down. Instead of a discrete approach, engineers may find integrated power sequencing or a PMIC-based alternative more suitable.

For ease of implementation, the LM3880 (a functional block diagram of this component is shown in Figure 1) can be specified for power sequencing purposes (the device shutdown procedure follows the same sequence and timing intervals as the power-up, but in reverse order). Thanks to its three open-drain output markers (which are held low at the start of power-up), it has the capacity to generate trigger signals for up to three voltage rails, with the option of cascading two sequencer ICs to provide six sequenced rails. The PMIC incorporates its own precision trigger input, which connects to an internal comparator with a 1.25 V reference, allowing engineers to configure the power-up sequence to begin as soon as a logic signal is received or when another voltage rail reaches a specific predetermined level. A capacitor can be connected to the trigger input to introduce a delay.
When activation is successful, the first output flag is confirmed after a preset delay (programmed into the EPROM during the OEM production process). The same amount of time then elapses before the second flag is confirmed, and again until the third and final flag is confirmed. Six preset timing designators are available, offering delays ranging from 2 ms to 120 ms.

The Maxim MAX16029 is a monitoring device that also offers capacitor-adjustable time delay. It can be used to sequence up to four voltage rails with a single PMIC. This manufacturer also offers sequencing devices that allow engineers to define synchronization via PMBus interfaces and thus star-connect multiple units to handle large numbers of voltage rails.

The fact that sequencing technology incorporates multiple power elements allows engineers to benefit from significant reductions in board utilization, as well as from overall less complex systems. The PMIC TPS65916 has five integrated configurable step-down converters that power the processor core, as well as the various memory and I/O pools present in a wide variety of microprocessors. Because they support adaptive voltage scaling, these converters are able to provide power-efficient operation that will not impact the system's allocated power. In addition, the PMIC also incorporates five low-current turn-off controllers to handle low-voltage or low-noise environments. The engineer can configure power-up and power-down sequences from programmable memory once, according to their needs.

Circumstances may necessitate a more complex sequencing process that requires consideration of additional voltage rails. In such cases, the power-on and power-off sequencing must be controlled in a more sophisticated manner, as specifying a simple sequencer or a general-purpose PMIC may not suffice; instead, the full programming capabilities offered by a microcontroller unit (MCU) may be required.

Microchip's well-known PIC16F1XXX series (shown in Figure 2) provides engineers with a power sequencing solution capable of managing multiple voltage rails. Its integrated, user-programmable firmware can be used to define the necessary timing. The device also offers extensive options for adjusting correct power criteria, as well as current rise and fall times. The 10-bit analog-to-digital converter digitizes each rail 16 times, then calculates an average value for accurate performance evaluation. The MCU's diagnostic capabilities provide rapid alerts in the event of a power supply failure.

Summary
As we have seen, it is crucial to ensure that the correct sequence is used when powering on or off electronic circuitry. This maintains long-term operational integrity and does not compromise system reliability. Available options range from basic sequencers to feature-rich PMICs and fully programmable MCUs. Given the wide variety of options on the market, it is simply a matter of evaluating which sequencing method is best suited to the main design objectives (whether it be maximizing performance, reducing the bill of materials cost, addressing space constraints, minimizing system power consumption, etc.) and then acquiring the necessary devices.

Author: Mirko Bernacchi, Mouser Electronics

 
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