In the era of software-defined vehicles (SDVs), automotive system-on-a-chips (SoCs) require high performance to run multiple applications simultaneously, as well as scalability through chiplets. They must also meet stringent functional safety requirements. As multi-domain SoCs grow in size and complexity, maintaining automotive-grade quality becomes more challenging. Furthermore, increased performance leads to higher energy consumption, making improved efficiency and safety essential. To address these needs, Renesas has developed the following technologies:
1. Functionally Secure Chiplet Architecture
To meet functional security requirements, Renesas has developed a proprietary architecture capable of supporting ASIL D even in chiplet configurations. By combining the standard UCIe interface with a proprietary RegionID mechanism, interference between hardware resources is avoided when multiple applications run concurrently, achieving functional independence (FFI).
Since conventional UCIe interfaces do not transmit RegionIDs between chips, Renesas has developed a method to map them to the physical address space and transmit them in an encoded form. This enables secure access control by the memory management unit (MMU) and cores in real time. Furthermore, a transmission speed of 51.2 GB/s has been achieved, approaching the transfer limit within a SoC.
2. Advanced AI capabilities with automotive quality
Renesas has developed a 3nm SoC that improves the performance of neural processing units (NPUs) while maintaining automotive-grade quality. To reduce clock latency caused by the increased size of the NPUs, the clock architecture was redesigned using mini-component generators (mCPGs) at the submodule level.
To ensure zero-defect quality, test circuitry was integrated into the hierarchical clock architecture, synchronizing test and operational signals. This enables unified phase adjustments and guarantees high reliability even in large-scale SoCs.
3. Advanced Energy Control and Monitoring:
Renesas has developed energy management technology with over 90 power domains, enabling precise control from milliwatts to tens of watts.
Two types of power switches are introduced:
Ring PSW: reduces inrush currents;
Row PSW: balances impedance.
This reduces voltage drops (IR drop) by approximately 13%.
To comply with ASIL D:
Dual Core Lock Step (DCLS) configuration is employed.
Loopback monitoring is implemented in the switches.
Voltage measurement is performed using a thermally resistant DVMON.
These improvements increase aging tolerance and safety.
These technologies are implemented in the R-Car X5H SoC, designed for multi-domain ECUs. With it, the evolution of SDVs is accelerated, enabling autonomous driving, digital cockpits, and more.
