The introduction of FIL adds to the comprehensive set of HDL verification options that EDA Simulator Link provides for algorithms created in MATLAB and Simulink. FPGA-based verification delivers significantly higher runtime performance than is possible with HDL simulators and increases confidence that the algorithm will work in the real world.
Key product features include the ability to:
- Verify HDL implementations of MATLAB code and Simulink models using FPGA development boards for Spartan and Virtex class devices, including the Virtex-6 ML605 development board.
- Verify HDL implementations of MATLAB code and Simulink models using cosimulation with Mentor Graphics ModelSim, Mentor Graphics Questa, and Cadence Design Systems Incisive Enterprise Simulator.
- Generate TLM 2.0 components for use in virtual prototyping environments in SystemC.
