With these two products, MathWorks now provides HDL code generation and verification using MATLAB and Simulink.HDL Coder generates portable, synthesizable VHDL and Verilog code from MATLAB functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. As a result, engineering teams can now immediately identify the best algorithm for hardware implementation. Traceability between Simulink models and the generated HDL code also supports the development of high-integrity applications that comply with the DO-254 standard and other standards
HDL Verifier now supports HIL verification for FPGAs for Altera and Xilinx FPGA boards. HDL Verifier provides cosimulation interfaces that link MATLAB and Simulink with HDL simulators such as Cadence Incisive, Mentor Graphics ModelSim, and Questa. With these capabilities, engineers can quickly verify whether their HDL implementation matches MATLAB algorithms and Simulink system specifications.
