They enable I3C control plane networks with multiple initiator controllers, such as the CPU and motherboard management controllers (BMCs), to support targets across a large, full-speed physical network by improving signal integrity and reducing capacitive loading. They also support heterogeneous designs by providing I/O level shifting and protocol translation for mixed I2C/SMBus and I3C networks.

The MIPI I3C® bus is a scalable control bus interface for connecting peripherals to the processor or other management controllers. It offers advantages of high performance, improved reliability, very low power consumption, and low electromagnetic interference (EMI). All of these advantages enable new system functionalities, such as advanced telemetry, fault recovery, sideband security, component authentication, and faster boot times.

Current system designs typically use the legacy I2C protocol and simple field-effect transistor (FET) switches to connect initiator and target devices on a motherboard. This approach cannot be scaled to I3C speeds, fundamentally limiting system management to the most rudimentary capabilities. Renesas' new family of I3C smart switches enables the expansion from two initiator (upstream) ports to four, eight, or more destination ports at full speed with full protocol awareness and compliance. The new Renesas family also provides seamless translation between I3C and I2C devices, enabling complete plug-and-play compatibility of legacy devices in the control plane network. The I3C smart switch is the result of close collaboration between the Renesas and Intel teams, beginning with the initial concept, specification definition, and other pre-silicon activities. This collaboration continued through post-silicon activities, including software development and component- and system-level validation.

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