As part of their long-standing strategic alliance, NVIDIA and Siemens have achieved a breakthrough previously thought impossible: capturing tens of trillions of cycles in just a few days, leveraging the scalable, performance-optimized hardware architecture of the Veloce proFPGA CS along with NVIDIA's optimized chip architecture.
“NVIDIA and Siemens are collaborating in multiple areas, especially in advancing hardware-assisted verification methodologies and FPGA-based prototyping, to meet the verification requirements of complex AI and machine learning SoCs,” said Jean-Marie Brunet, senior vice president and general manager of hardware-assisted verification at Siemens Digital Industries Software.
“Veloce proFPGA CS addresses these challenges by combining a flexible and scalable architecture with an advanced, easy-to-use deployment and debugging flow, offering an optimal solution for both single-FPGA IP validation and chiplet designs with billions of gates.”.
For his part, Narendra Konda, vice president of hardware engineering at NVIDIA, noted: “As AI and computing architectures become more complex, semiconductor teams need high-performance verification solutions that enable them to validate massive workloads and accelerate time to market. Integrating our architectures with Veloce proFPGA CS allows us to capture trillions of cycles in days, ensuring the reliability of the next generation of AI.”
FPGA-based prototyping systems offer high speed and allow pre-silicon verification workloads to be run in a fraction of the time required by simulation or emulation. However, current AI and ML designs demand even greater capacity due to the increasing complexity of both hardware and software.
To meet these demands, comply with market deadlines, and ensure reliability, the ability to execute trillions of cycles in a short time has become a critical requirement. Traditional verification tools, such as simulation and emulation, do not scale beyond millions or, at best, a few billion cycles in a reasonable timeframe.
