One of the key innovations is the development of an artificial intelligence agent to automate the correction of errors detected during design rule checks (DRCs) in custom and digital integrated circuits. The technology combines Siemens' Calibre, Aprisa, and Solido tools to identify, analyze, and correct design rule violations, reducing the manual intervention required during this phase of development.
Agentic AI applied to semiconductor design
Siemens and TSMC are also working on design workflows based on the Fuse EDA AI System and the Fuse EDA AI Agent. These technologies are geared towards the autonomous execution of lengthy EDA processes and the verification of the results obtained during their execution.
The agents can handle multi-stage design tasks, coordinate operations between different EDA tools, and verify results throughout the process. Fuse EDA AI Agent also incorporates NVIDIA AI to optimize the processing of these types of workloads.
Among the applications developed is an automated workflow for DRC correction that uses Calibre, Aprisa AI, and Solido Fuse. The system analyzes design rule violations and provides contextual information to facilitate their diagnosis and correction. The collaboration also includes custom integrated circuit design capabilities using AI agents and automated place-and-route processes and digital implementation with Aprisa.
Support for TSMC 3DFabric and 3D IC designs
Another area of collaboration focuses on TSMC's 3DFabric three-dimensional integration technologies. Calibre 3DStack Advanced incorporates multi-machine support for antenna verification between chiplets, including compatibility with TSMC-SoIC, the wafer-level 3D stacking platform for integrated circuits.
Work is also underway on certification for CoWoS-L (chip-on-wafer-on-substrate with local silicon interconnect), an advanced packaging technology for systems integrating multiple components and chiplets. The Solido Simulation Suite, Calibre xACT, and Calibre 3DThermal tools are also involved in various workflows related to 3D IC design, multiphysics analysis, advanced packaging, and silicon photonics.
Thermal analysis of advanced chips
Thermal analysis is another area of development. Calibre 3DThermal is certified to perform static and transient thermal analyses of TSMC 3DFabric technologies. The tool is also certified to perform these analyses with the TSMC A16 process and is enabled for reference thermal flux of wafer-level systems.
Siemens and TSMC are also working on support for TSMC-COUPE (Compact Universal Photonic Engine), as well as expanding compatibility with 3Dblox to facilitate joint chip and package design workflows.
Silicon photonics
The collaboration extends to the design, implementation, and verification of silicon photonics-based devices. This work utilizes tools such as Innovator3D IC Integrator, Calibre 3DStack, Solido Simulation Suite, L-Edit, and Calibre Interactive to support features related to TSMC-COUPE. Solido Simulation Suite also supports PAM4 measurements associated with this technology for optical transceiver interfaces. Simultaneously, the validation process for Calibre 3DThermal for TSMC-COUPE continues.
Certification for processes A14, A16 and N3C
The collaboration between the two companies also includes the certification of EDA tools for TSMC's most advanced manufacturing processes. Calibre nmDRC, Calibre nmLVS, Calibre xACT, and Calibre PERC have been certified for the TSMC A14 node.
For its part, Solido Simulation Suite has SPICE accuracy certification for TSMC N3C, A16, and A14 technologies, with applications in the verification of analog circuits, RF, and memories. The work also includes simulation functions designed to analyze integrated circuit aging, real-time self-heating, and safe operating conditions.
The mPower tool is certified to perform voltage drop and electromigration (IR/EM) analysis at the transistor level in the TSMC N2P and N3C processes. Aprisa and mPower are also continuing their certification work for the A14 technology.
The expansion of this collaboration reflects the increasing incorporation of artificial intelligence and automation into EDA flows, especially in processes where the complexity of designs, the integration of chiplets, and advanced manufacturing nodes increase the number of checks and operations required before taking a design to manufacturing.
