Twin BiCS FLASH achieves a superior program slope and a larger program/erase window in a much smaller cell size compared to conventional circular charge trap (CT) cells. These attributes make this new cell design a promising candidate to surpass four bits per cell (QLC) for significantly higher memory density and fewer stacking layers. This technology was announced at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, CA, on December 11.
3D flash memory technology has achieved high bit density at a low cost per bit by increasing the number of stacked cell layers and implementing multi-layer stacking deposition and high aspect ratio etching. In recent years, as the number of cell layers has exceeded 100, managing the trade-offs between etching profile control, size uniformity, and productivity has become increasingly challenging. To overcome this challenge, KIOXIA has developed a novel semicircular cell design by splitting the gate electrode in the conventional circular cell. This reduces the cell size compared to the conventional circular cell, enabling higher-density memory in fewer cell layers.
The circular control gate provides a larger program window with reduced saturation problems compared to a flat gate due to the curvature effect, where carrier injection through the tunnel dielectric is improved while electron leakage to the block dielectric (BLK) is reduced. In this split-gate cell design, the circular control gate is symmetrically divided into two semicircular gates to take advantage of the significant improvement in program/erase dynamics. As shown in Figure 1, the conductive storage layer is employed for high charge capture efficiency along with high-k BLK dielectrics, achieving a high coupling ratio to maximize the program window, as well as reduced electron leakage from the gate, thus alleviating the saturation problem.
The experimental program/erase characteristics in Fig. 2 reveal that semicircular FG cells with high-k BLK exhibit significant gains in program slope and program/erase window compared to larger circular CT cells. It is expected that semicircular FG cells, with their superior program/erase characteristics, will achieve comparatively narrow QLC Vt distributions at a small cell size. Furthermore, the integration of the low-trap Si channel enables more than four bits per cell, for example, PLC (Penta-Level Cell) as shown in Fig. 3. These results confirm that semicircular FG cells are a viable option for achieving higher bit density.
In the future, KIOXIA's research and development efforts focused on flash memory innovation will include the continued development of Twin BiCS FLASH and the exploration of its practical applications. At IEDM 2019, KIOXIA also announced six other papers highlighting the company's intensive R&D activities in the flash memory field.
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[1] Source: KIOXIA Corporation, as of December 12, 2019.
