Over the past few months, the De-RISC project has been able to define the requirements that define its technology: the software architecture, the System-on-Chip architecture, and the hardware platform. This was the first step in beginning the project's technical activities.
Regarding the hardware, the project has developed the first version of the De-RISC MPSoC platform and the Monitoring Unit, integrating observability capabilities (Cycle Contention Stack, Request Duration Counter) and controllability capabilities (Maximum-Contention Control Unit).
On the software side, the consortium successfully ported the first prototype of the XtratuM XNG hypervisor and LithOS, the paravirtualized guest operating system, to the NOEL-V processor. Validation activities, which will generate evidence for the platform's commercialization, have already begun and are expected to be evaluated through the implementation of various use cases, incorporating aviation and space-based onboard requirements from the outset.
The implementation of full virtualization, spatial prequalification activities, and shared resource containment analysis to minimize core interference will be the next challenges De-RISC addresses. Software tasks, on the other hand, will include migrating RTEMS, an open-source real-time operating system, as the guest operating system for XtratuM XNG and updating software development tools to support XNG and LithOS in NOEL-V.
In recent months, two relevant organizations, RISC-V International and HIPEAC,
The future prospects for De-RISC appear promising, as reflected in the interest shown by various companies not only in the space market but also in the aerospace and automotive industries. The final results of this project will have to wait until March 2022, when the consortium will be ready to provide this complete hardware and software platform to the aerospace market.
About De-RISC:
De-RISC (Dependable Real-time Infrastructure for Safety-critical Computer) is a European project falling under the category of “Innovation Action.” It will run for 30 months and is co-financed by the European Commission. This project began in October 2019 and has a budget of €3,440,625. The project will deliver a market-ready hardware and software platform based on the RISC-V instruction set, commercializing a multi-core integrated-chip system based on this ISA designed by Cobham Gaisler, and a system with time and space partitioning based on the fentISS XtratuM hypervisor.
The consortium consists of four partners with extensive experience in the aerospace sector with safety-critical systems. The XtratuM hypervisor from fentISS (Spain) has been selected for several space missions, including the OneWeb satellite constellation, the generic satellite for the PLATINO constellations, ARGOS-NEO ANGELS, EyeSat, MERLIN, JUICE, and MMX. The LEON series of processors, developed by Cobham Gaisler, has been used in various ESA missions. The Barcelona Supercomputing Center is a leading research center in Europe and has collaborated with Gaisler and Thales on European projects such as SAFURE and PROXIMA. Finally, Thales Research and Technology.
