Signals become more resistant to noise and distortion when they have a greater amplitude. This is why the most widespread industry standard for the analog signal range is ±10 V. This article explains why the latest generation of successive approximation analog-to-digital converters (ADCs) are not compatible with this signal range and why modern ADCs are returning to this standard.
ADCs with a successive approximation register function like a balance [1, 2]. As shown in Figure 1, the comparator evaluates whether the input voltage Vin captured by the sample-and-hold (S&H) capacitor is higher or lower than the voltage generated by a capacitive digital-to-analog converter (DAC or CDAC). The DAC approximates the input voltage with an additional bit of precision per clock cycle.
The SAR ADC is the most widely used converter, although it is neither the fastest nor the most accurate. The advantage of the SAR ADC compared to the high-resolution delta-sigma converter is its ability to take an instantaneous sample of the original signal, allowing the signal to be sampled at a precisely defined moment. In industrial process control, this is often important.
Furthermore, the SAR ADC achieves higher conversion rates with similar power dissipation. Compared to pipeline converters, the SAR ADC offers better noise performance and consumes significantly less power, an important consideration in battery-powered systems or where power dissipation is limited by the application.
Industrial applications are often exposed to harsh environmental conditions, making a wide analog signal range (±10V or more) preferable for signal reinforcement. Unfortunately, semiconductor processes are generally incompatible with this voltage range due to the breakdown voltage of the internal transistors. This article describes the history of the SAR converter and new high-voltage solutions using specialized analog processes, and also presents the outlook for the next generation of products.
Limitations of High-Voltage ADCs in the Previous Generation:
Until the mid-1990s, ADCs allowed a bipolar input voltage range of ±5 V or ±10 V. This was achieved using 2 mm and 3 mm CMOS processes that included highly linear resistors. A typical example is the Burr-Brown ADS7809. Table 1 shows some specifications. Differential nonlinearity (DNL) allows for true 16-bit performance, but the conversion speed is slow and power consumption is high.
This is due to the required transistor size. The comparator input, for example, requires a low-noise differential pair. The noise of MOS transistors is a function of the transconductance gm, which is itself a function of the ratio of the transistor's width W to its length L and the current flowing through it. The minimum length is limited by the process; the width must be large and the current high.
The size of the devices will also cause inherent parasitic capacitance. For example, the gate capacitance of the comparator's second gain stage will limit the speed of the first differential pair and therefore also limit the comparator's conversion speed. Thus, converter design must involve a trade-off between power, speed, and noise.
The large transistors of the previous generation of ADCs also required large wafer sizes, resulting in high wafer production costs and lower profit margins. Furthermore, the low speed led to long testing times, making high-performance ADCs expensive. The large wafer size also necessitated large package formats, such as the dual-row package (DIP) or the wide-body surface-mount IC (SOIC). Consequently, ADC research and development shifted away from high-voltage designs and processes and toward CMOS processes with shorter gate lengths.
The first 5V generation:
The first 16-bit ADC on a 5V process (the Burr-Brown ADS8320) was named Product of the Year in 1998. Performance with respect to noise was improved thanks to the better gm of the transistors. Power consumption was significantly reduced due to the use of a lower supply voltage and smaller parasitic capacitors. This enabled the use of SAR ADCs in new applications such as portable and battery-powered devices, including touchscreen products.
Unfortunately, the small LSB (least significant bit) size made the converter more sensitive. Designs had to address thermal issues and package changes, resulting in reduced differential linearity to 14-15 bits and integral linearity to 13-14 bits (see also Table 2).
The second generation of 5V ADCs
featured new architectures designed to create more robust products and reduce noise and power consumption. One such architecture is dynamic error correction [3], which allows for errors during most significant bit (MSB) decisions, while the comparator is under heavy load and the reference source must recharge large capacitors. These errors are corrected during least significant bit (LSB) decisions, when lower-level signals reduce settling effects. This improved the linearity of the second generation of SAR ADCs over a 5V process.
New reference designs with external compensation capacitors [4] further reduced power consumption. An optimized DAC design improved noise performance. Using a Texas Instruments (TI) ADS8329, a signal-to-noise ratio (SNR) of 93 dB was achieved at a conversion rate of 1 MSPS and a power consumption of 39 mW with a 5 V supply or 15.5 mW with a 2.7 V supply (see Table 3).
Fully differential ADC architectures (see Figure 2), such as the TI ADS8482, were presented to double the input interval along with the LSB size and signal-to-noise ratio. Theoretically, a 6 dB improvement can be obtained. Increasing the resolution to 18 bits further reduces quantization noise, allowing a signal-to-noise ratio of 100 dB to be achieved.
Unfortunately, further reducing the transistor length will not necessarily lead to a reduction in noise. This is because the transistor noise of the comparator and the reference is no longer dominant. Reducing the input voltage... The parameter that becomes dominant is the so-called kT/C noise. This is thermal noise generated during sampling by the input switch's conduction resistance Ron. The noise density of a resistor nRon is described in [5].
(1)
In equation (1), k represents the Boltzmann constant and T the absolute temperature. The bandwidth of this thermal noise is limited by the switching conduction resistance and the ADC's sampling capability Cs. The effective noise bandwidth [5] can be calculated as follows:
(2)
The effective (rms) voltage of the sampling noise Vsrms is therefore:
(3)
As shown in equation (3), sampling noise depends only on the size of the sampling capacitor. By switching to a more modern process where the transistor length is reduced by a factor of x, the maximum permissible supply voltage would be reduced by that same factor of x. This lower supply voltage would reduce the input voltage range and therefore the size of an LSB by that same factor of x. If the sampling noise must remain constant with respect to an LSB, the sampling capacitor must be increased by a factor of x2.
This would not only result in a significant increase in wafer size but would also jeopardize the process of recharging the DAC capacitors from a negative reference (almost always ground) to a positive reference. Recharging the capacitance by a factor of x2 at a reference voltage x times lower would increase the reference current by a factor of x. The power consumption would remain constant, since a current x times higher would be maintained up to a reference voltage x times lower. The only advantage would come from the comparator design (see Figure 3).
It does not appear possible to significantly improve performance by reducing the gate length. The key elements in the analog design focused on developing a new process that kept the transistor length at 0.5–0.6 mm and added very specific features for high-performance analog products.
High-Performance Analog Process Development:
A crucial aspect is the use of properly matched resistors, which also exhibit low temperature drift throughout their lifespan. These resistors enable the design of high-performance R-2R digital-to-analog converters, such as the TI DAC8831. Furthermore, if the resistor's voltage coefficient is low, it becomes possible to create series DACs with very low integral nonlinearity, such as the TI DAC8558.
An extremely low metal substrate allows for the design of complex digital interfaces and functions. Previous generation products generally had very simple series or parallel inputs or outputs. New functions were added, controlled by an internal register map. Electrical regulation, also controlled by the register map, was implemented using electrical fuses or one-time programmable memories. Some products even implemented various interfaces controlled externally via pins.
Furthermore, a BiCMOS process yields good bipolar transistors, which are important for amplifier and reference circuit designs. Such a process requires a buried N-layer that isolates a P-well from the substrate (see Figure 4). As a side effect, these isolated P-well areas are used to isolate the NCH transistor array from the substrate. In this way, the substrate can be isolated from digital circuitry noise, and the sensitive analog circuits can be isolated from general substrate noise.
The most interesting are the high-voltage transistors, which are implemented using a dual-gate process. 36 V can be applied between the drain and source, as well as between the gate and source. The combination of high-voltage and low-voltage transistors can be used for interesting products such as the next generation of high-voltage ADCs.
A New Generation of High-Voltage ADCs:
Although 5V ADCs achieve excellent noise performance, they are not the most suitable for industrial process control. Having a low-noise converter is not enough; a robust analog section is also required to adapt the incoming signal under these harsh conditions. ±10V input signals are inherently four times more robust compared to simple 5V systems. This is why high-voltage ADCs remain of great interest. A
new generation of high-voltage ADCs will benefit from the components of this new process. There are two approaches. One involves using resistors with low drift and low voltage coefficient. The ±10V input signal can be internally split and shifted to the 0-5V range. This allows the signal to be processed with 5V transistors, taking advantage of the higher speed, lower noise, and lower power consumption of these low-voltage transistors. A typical example is the TI ADS8515. However, performance was improved with new architectures and the new process. Table 4 compares the specifications of the previous generation (ADS7809) and the new generation (ADS8515).
This implementation has two drawbacks. First, it forces a direct current from the input signal, so high-impedance input sources will generate gain errors. To keep this current low, the internal resistance must be high, which limits the ADC's input bandwidth. This automatically requires longer sampling times, resulting in lower conversion speeds.
In the second approach, the high-voltage input signal is sampled directly into the sampling capacitor using high-voltage transistors. The ADC's capacitive DAC then divides the signal using SAR. This method also has disadvantages.
Although the capacitors offer an excellent voltage coefficient, it will still affect the ADC's overall linearity. At high voltages, this is especially true for the squared voltage coefficient. If a 10 V signal is stored in the capacitor and the squared voltage coefficient is approximately 1 ppm/V², the sampling capacitor's variation is 100 ppm at the extremes, but not in the middle of the scale. The integral nonlinearity extends to several LSBs.
The second drawback is caused by the high conduction resistance Ron and high parasitic capacitance Cmsw of the high-voltage input switches. Both effects are nonlinear with respect to the input voltage and do not affect DC performance. However, AC signals are affected by distortion due to the input voltage-dependent delay Ron·(Csw+Cs) of the sampling circuitry. Initialization (see Figure 5), where the input switch gate tends toward the input signal plus a constant voltage and the assembly is short-circuited to the input, reduces total harmonic distortion but requires extensive circuitry and increases wafer size.
Nevertheless, sampling with high-voltage switches appears to be the technique that will be used in future products. New design architectures and further process improvements will be developed to overcome the aforementioned problems.
Outlook
In summary, the new high-voltage products provide significant improvements in speed, power, and noise. Unfortunately, two major limitations remain. The high-resistance sampling switch, which also exhibits significant parasitic capacitance, affects total harmonic distortion (THD) at signal frequencies above 100 kHz. Furthermore, the capacitor's voltage coefficient generates integral nonlinearity independent of the input frequency.
It appears that further advancements are needed to address the THD issue. On the other hand, it is time to develop a regulation solution for the integral nonlinearity, especially since all other DC specifications are adjustable, such as differential nonlinearity, offset [6], gain [7], and even common-mode rejection.
Moreover, the high input voltage should enable designs that improve noise performance in terms of signal-to-noise ratio. Products with a 106 dB signal-to-noise ratio are expected to appear in the future.
References
[1] F. Oehme, M. Huemer and M. Pfaff, Elektronik und Schaltungstechnik, Carl Hanser Verlag, ISBN 3-446-40694-8, 2006.
[2] Rudy J. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, Springer Netherlands, ISBN 1-4020-750-6, 2003.
[3] Chakravarthy Srinivasean, Kiran M. Godbole, Error correction architecture to increase speed and relax current drive requirements of SAR ADC, patent US6747589, Texas Instruments, 2004.
[4] Frank Ohnhaeuser, Mario Huemer, Reference generation for A/D converters, CD-ROM proceedings of the International Symposium on Signals, Systems and Electronics (ISSSE2007), Montreal (Canada), August 2007.
[5] P. Gray, R. Meyer, Analysis and Design of ANALOG INTEGRATED CIRCUITS, John Wiley & Sons, Inc., ISBN 0-471-57495-3, 1993.
[6] Frank Ohnhaeuser, Miroslav Oljaca, Offset error compensation of input signals in analog-to-digital converter, patent US6433712, Texas Instruments, 2002.
[7] Robert Seymour, Method and circuit for gain and/or offset correction in a capacitor digital-to-analog converter, Patent US6922165, Texas Instruments, 2005.
Author:
Frank Ohnhauser. Texas Instruments
