Good inter-channel isolation is critical for maintaining performance in beamformer integrated circuits (BFICs). Inter-channel gain settings in phased-array applications can vary significantly to achieve the desired sidelobe reduction and muting (a 30 dB difference is not unusual). As shown in Part 1, modern BFICs typically have multiple parallel on-chip RF paths leading to pins located on the same edge and/or corner of the IC package, often with all inputs (or outputs) also on the same edge. The challenge, therefore, is to route the multiple RF lines to and from these closely spaced pins on the printed circuit boards (PCBs) while maintaining sufficient isolation between the lines.
The second part of this series of articles analyzes how the amount of insulation between transmission lines affects BFIC performance, provides general guidelines on choosing the best transmission line topology based on application insulation requirements and BFIC geometries, and explains the best way to distribute closely spaced transmission lines near the BFIC. This article gives dimensions primarily in thousandths of an inch (1000 thousandths of an inch equals 1 inch). To convert from thousandths of an inch to millimeters, multiply by 0.0254.
Isolation: Transmission Line to Transmission Line.
On any PCB, two adjacent transmission lines will have some degree of coupling between them, either electrically and/or through electric and magnetic (EM) fields, resulting in non-infinite isolation. There are large differences in isolation performance between the line topologies discussed in Part 1. Top-layer routing typically has worse isolation than buried lines due to field coupling. Beyond the chosen line topology, the dominant factors affecting isolation are the operating frequency, the distance between lines, and the parallel routing distance of the lines. Furthermore, if a buried topology, such as a band line, is used, any transition to the top layer must be carefully designed to maintain good isolation.
Figure 1 shows a Keysight RFPro EM simulation of isolation versus frequency for two pairs of transmission line topologies: grounded coplanar waveguide (GCPW) and buried GCPW. The center-to-center spacing of each line pair was set at 60 mils, with a parallel routing distance of 200 mils. Six-mil earth conductors spaced 25 mils center-to-center were used for fencing on both sides of each line. GCPW has worse simulated isolation than buried GCPW. Clearly, a buried topology should be chosen when isolation is critical.
Figure 1. Simulated insulation of GCPW and buried GCPW.
GCPW vs. Buried GCPW: The Difference 15 dB of Isolation Can Make.
Poor isolation between transmission lines on a printed circuit board (PCB) can be especially problematic in applications where there is a large difference between the signal levels on the respective traces. In a phased array system, if two adjacent variable amplitude and phase (VAP) blocks operate at minimum and maximum attenuation, stray signal coupling will degrade the linearity of the VAP gain control function on the more attenuated path. This behavior was observed in the ADAR3001, a 4-input, 4-output BFIC (similar to the one shown in Figure 1 of Part 1), on a PCB with GCPW transmission lines. The PCB was redesigned with buried GCPW to increase isolation between lines.
RMS gain error is an abstract figure of merit that indicates the nonlinearity of the gain control. In this case, the RMS gain error was measured on both versions of the PCB. Figure 2a shows the RMS gain error of the original PCB with GCPW, while Figure 2b shows the RMS gain error of the redesigned PCB with buried GCPW. In Figure 2a, the RMS gain error is significantly worse when the VAP's stepped digital attenuator (DSA) is used across its entire range. This is to be expected, as the application is more susceptible to poor isolation when the difference between the DSA attenuations is at its maximum.
The improved line-to-line isolation of the buried GCPW board significantly improved the RMS gain errors, aligning with the simulations and reflecting the BFIC's actual performance. These results demonstrate that even a moderate improvement in isolation of 15 dB at 30 GHz can drastically affect measured performance.
Figure 2. BFIC rms errors on a PCB with (a) GCPW lines versus a PCB with (b) buried GCPW.
Isolation of Two Parallel Lines
: It is generally assumed that the band-line topology offers the best isolation of the topologies mentioned. To test this assumption, an experimental board was fabricated to see how much isolation over frequency could be achieved with a band-line topology. An 8-mil-wide band-line design was used on layer 2 over 8-mil Rogers 4003C dielectrics (layer 1 to layer 2) and 8-mil Rogers 4450T dielectrics (layer 2 to layer 3). The center-to-center distance of the line pair was 76 mils, and the parallel run length was 300 mils. These distances were chosen to roughly emulate the average pitch between the RF pins of many BFICs and the subsequent run that the lines must take before exiting to coaxial connectors or other devices. Each line had its own rail fence with 10-thousandths of an inch rails and an 18-thousandths-of-an-inch center-to-center pitch. Figure 3a shows the strip line arrangement in layer 2 (the layer 1 and layer 3 ground planes that enclose the strip line on either side of the Rogers dielectrics are not shown). The insulation measurement shown in Figure 3b clearly demonstrates that an uninterrupted strip line with a narrow rail fence provides optimal performance and should be used when insulation requirements are very high.
Figure 3. Design of an experimental plate with band line design (layer 2 is shown) and (b) the plate isolation results.
The isolation graph shows noise because the line pair isolation is at the limit of the vector network analyzer's (VNA) measurement capabilities. The average isolation across all frequencies is greater than -80 dB. The drop in isolation that occurs at approximately 26 GHz is due to the VNA.
Isolation of Two Parallel Bandlines with Back-to-Back L1-to-L2 Vias.
On the same experimental board presented in the previous section, another pair of bandlines was designed with the same attributes as before (line geometry, via placement, line spacing, and parallel run length), but a pair of transition vias (or consecutive layer 1-to-layer 2 vias) was added to each line to see how the insulation degrades upon transition to the top layer, as shown on the left side of Figure 4a. The top layer routing was kept short, at 14 thousandths of an inch between the centers of the vias, as shown in the enlarged image on the right side of Figure 4a.
The insulation on these bandlines with back-to-back transition vias (back-to-back vias from layer 1 to layer 2) was measured and found to be degraded compared to the lines without transition vias, as shown in Figure 4b. This experiment highlights the importance
Figure 4. (a) Breadboard layout with enlarged (left) and reduced (right) views of a pair of band lines with consecutive transition vias and (b) measured isolation of the breadboard with transition vias.
Guidelines on Routing Multiple RF I/Os
Many integrated circuits, particularly RF beamformers, have a high number of RF I/Os, which makes routing and maintaining good RF performance difficult. In addition to careful selection and design of the transmission line topology, proper grounding via fencing extending to the device is critical to maintaining RF performance, particularly isolation.
Which Transmission Line to Use:
The decision on which transmission line to use should be based primarily on the isolation requirements and the BFIC geometries. For example, if the isolation only needs to be around -40 dB, then a GCPW can be safely used. If the isolation needs to be around -65 dB, then a band line is necessary. Next, the BFIC geometry must be considered, primarily the size of each pin, the pitch between pins, and the distance between the RF pins. For example, if the BFIC is a BGA with a solder ball diameter of 5.5 mils/0.22 mm, a pin spacing of 10 mils/0.4 mm, and a distance between the nearest RF pins of 30 mils/1.2 mm, and if the isolation requirement is -65 dB or higher, the BFIC geometries could accommodate a symmetrical band line with approximate dimensions of: 6 mils line width, 6 mils dielectric thickness (above and below the line), and a 10 mil ground side clearance, assuming a dielectric constant of around three. The general rule for band lines is that the ground side clearance should be approximately twice the line width; smaller clearances begin to affect the line impedance. Smaller distances between RF pins would require a thinner wire, while a larger distance between RF pins would allow for a wider wire. As seen in Part 1, the latter is preferable, as it increases the likelihood of achieving 50 Ω during manufacturing.
Routing near the device:
When using a band line, care must be taken when transitioning to the device pin in the upper layer, as this transition can significantly degrade isolation if proper grounding vias are not used. To achieve the greatest possible isolation, the ground wall of the vias should extend around the end of the band line at the device transition, as shown in Figure 5. This extends the critical ground wall required for optimal isolation performance. The device should also have ground pins, protrusions, and/or ground paddles surrounding the signal pin that roughly align with the extended ground wall vias.
Figure 5. Vias extending around the transmission line at the device and running to a single row of vias between lines.
RF I/O pins located close together may not provide enough area for each transmission line to maintain the same via fence to the device. Depending on the available area, typical via fence options are:
1. Use smaller vias if they do not violate the manufacturer's aspect ratio standards for dielectric thickness.
2. Stagger the vias in a sawtooth pattern where there is a moderate amount of area if the absence of a via on one of the lines at the device interface does not degrade the isolation.
3. As shown in Figure 5, run to a single row of vias between lines using a larger via size, maintaining the same distance between the edges of the via holes as with the smaller vias; this maintains isolation performance.
4. Run to a single row of vias between lines using the same via size when the spacing between lines is very limited.
The decision of when and how to perform fanout depends largely on the location of the RF I/O pins relative to each other on the device.
The general rule is that fanout should be performed as early as possible to minimize parallel runs and thus maintain the greatest possible isolation. As seen in Figure 5, fanout can be performed immediately due to the relative positions of the RF I/O pins shown (and the pins not shown). However, Figure 6 shows the fanout of a 2-channel, 8-output device where each channel has a 1:4 switch as its output stage, driving four transmit lines of varying parallel run lengths. In this case, fanout was also limited by the non-RF I/O routing and associated circuitry on the north and south sides of the device, which restricted where and how the eight transmit lines could be routed.
Figure 6. Eight RF output fanout of a 2-channel device.
Conclusion:
The advent of high-frequency multichannel beamformers and other RF integrated circuits is making PCB design more complex, both in terms of transmission line accuracy and transition (as discussed in Part 1), and in maintaining the high inter-channel isolation necessary to sustain device performance (as discussed in Part 2). RF transmission line designs are undergoing a forced migration from surface-grounded coplanar waveguides to buried band lines, but even with buried band line designs, care must be taken to maintain isolation between adjacent traces by using closely spaced via fences that completely enclose the device pins. Furthermore, the rapid dispersion of closely spaced traces from the device, creating separation between traces, is helpful in maintaining high isolation.
About the author:
Joel Dobler is a senior product applications engineer in the Aerospace, Defense, and Communications Group, where he focuses on beamforming products but also supports vector modulators and programmable low-pass filters. He has worked for Analog Devices since 2006, supporting a wide range of RF products, including logarithmic and RMS detectors, digital and analog variable-gain amplifiers, mixers, and I/Q demodulators. He received his Bachelor of Science in Electrical Engineering from Washington State University in 2005 and his Master of Science in Electrical Engineering from Portland State University in 2006.
