Quartus II Subscription Edition version 10.1 includes a beta version of Qsys, Altera's next-generation system integration tool, which features the market's first network-on-chip interconnect optimized for FPGAs. Qsys offers memory allocation and streaming support that nearly doubles the capabilities of Altera's SOPC Builder tool, improves system scalability for large FPGA designs, and provides support for standard interfaces (Avalon® and AMBA® AXI™ standards, as well as ARM's AHB™, etc.).
Qsys enables the design of high-performance FPGA-based systems by utilizing a network-on-chip (network-on-chip) interconnect architecture. Qsys applies network theory to on-chip communications to deliver improved performance compared to conventional bus and switch-based interconnects. This method, which packages all memory-mapped and current-streamed data, offers higher throughput for the same latency and resource utilization. Qsys also provides an automatic pipelining function to further increase the system's fMAX.
Designs that incorporate powerful intellectual property (IP) or a large number of system components take advantage of Qsys' hierarchical design flow. The tool enables system scalability by dividing large FPGA designs into multiple subsystems. This hierarchy allows designers to easily manage each subsystem and provides them with the ability to add additional subsystems to the design with minimal impact on system performance.
Qsys expands the amount of IP available for FPGA-based system-level design by supporting standard interfaces such as Avalon and AMBA AXI, as well as ARM's AHB. The tool provides designers with maximum flexibility through automatic handling of connections between multiple interface standards. This capability allows users to leverage IP cores with multiple interfaces in a single design. The initial release of Qsys supports the open standard Avalon. Other standard interfaces, such as ARM's AMBA AXI and AHB, will be supported in future releases.
"Productivity remains a top priority for our customers," said Chris Balough, chief marketing officer for software, embedded, and digital signal processing (DSP) at Altera. "Altera's new Qsys tool leverages our decade-long experience as pioneers in FPGA-based switch fabric to deliver a substantial level of new features and capabilities that will enhance system-level design and IP reuse for our customers."
OEM agreement with Mentor
Graphics, providing Quartus II software customers with access to the latest version of the ModelSim® tool. New features in the ModelSim-Altera Edition and the ModelSim-Altera Starter Edition include a waveform editor and support for the Altera® IP simulator. The waveform editor supports a well-established method for quickly generating input stimuli for verification.
The features included in the Quartus II v10.1 software are:
• Support for new devices—This version offers full support for Altera’s new MAX® V CPLD device family announced today. Support for Altera’s new Arria® II GZ FPGA family and expanded support for the Stratix® V FPGA family are also added.
• Faster recompiles—Improvements to the software’s Rapid Recompile feature maximize designer productivity by reducing compilation time by an average of 65 percent.
• New external memory interface toolkit—The new toolkit helps designers get their boards ready faster by identifying calibration issues and measuring margins for each validation signal (DQ strobe, DQS).
• Improvements to Chip Planner and TimeQuest—Chip Planner now includes a new window so designers can easily view and plot multiple critical timing paths. TimeQuest adds a new feature to report timing closure recommendations so that designers can quickly identify and resolve timing closure issues.
