In the era of software-defined vehicles (SDVs), automotive system-on-a-chips (SoCs) require high performance to run multiple applications simultaneously and must offer scalability through chiplets, in addition to meeting functional safety requirements. As multi-domain SoCs for core computing grow in size and complexity, maintaining automotive-grade quality becomes increasingly difficult. Increased performance also raises energy consumption, making improvements in energy efficiency and safety crucial. To address these needs, Renesas has developed the following technologies:
Renesas has developed a new proprietary chiplet architecture that supports ASIL D even in chiplet configurations. By combining the standard UCIe die-to-die interface with a proprietary RegionID mechanism, the architecture prevents interference on hardware resources when multiple applications are running simultaneously, achieving Freedom from Interference (FFI). Since conventional UCIe interfaces do not allow RegionID transmission between dies, Renesas developed a method to map these identifiers to the physical address space, encode them in the UCIe region, and transmit them. This enables secure access control by the MMU and cores in real time, meeting functional security requirements between chiplets. Furthermore, a transmission speed of 51.2 GB/s was confirmed, close to the upper limit of intra-SoC transfer, ensuring scalability and security in high-performance automotive SoCs.
Advanced AI Capabilities and Automotive-Grade Quality:
Renesas has designed a 3nm SoC that improves NPU (Neural Processing Unit) performance while maintaining automotive-grade quality. NPUs have increased in size by up to 1.5 times compared to previous generations, which increases clock latency. To address this, Renesas redesigned the clock architecture by dividing the pulse generators (CPGs) into mini-CPGs (mCPGs) at the sub-module level, significantly reducing latency.
To ensure zero defects in automotive applications, the company integrated test circuitry into the hierarchical CPG architecture and unified the signal path for user and test clocks. In test mode, the upper and lower mCPGs are synchronized under a single clock source, enabling unified phase tuning and ensuring high reliability even in large-scale SoCs.
advanced
power gating technology with over 90 power domains, enabling precise control from milliwatts to tens of watts. Furthermore, it has divided the power switches (PSWs) into ring and row types to reduce voltage drops (IR drop), achieving an approximate 13% reduction compared to conventional designs.
To comply with ASIL D, the dual-core lock-step (DCLS) configuration controls master and verifier cores with independent switches and controllers. If one fails, the system detects the error through lock-step operation. Loopback monitoring of each PSW and a thermally resistant digital voltage meter (DVMON) are added, improving aging tolerance by 1.4 mV.
These technologies are being applied in the Renesas R-Car X5H for multi-domain ECUs. With the R-Car X5H, manufacturers can accelerate the evolution of SDVs by ensuring safety and enabling autonomous driving, digital cockpits, and more.
