The new version enhances the high-level design environment of Quartus II software, further simplifying traditional hardware development tasks so users can maximize productivity and take full advantage of the wide range of features offered by Altera devices. Quartus II version 12.1 strengthens its support for high-level design workflows by incorporating a Software Development Kit for OpenCL™, as well as improvements to both the Qsys system integration tool and the DSP Builder model-based design environment. This new version also includes other advancements such as a partial reconfiguration design workflow, new proprietary cores, and enhanced support for FPGAs and GPGAs on 28nm SoCs.
Accelerating System Development with High-Level Design Tools
Among the high-level design tools offered by Altera are C-based, IP-based, and model-based system-level design introduction tools. These tools enhance and simplify the development of today's advanced programmable systems, which include CPU cores, digital signal processing (DSP) blocks, and multiple IP subsystems. The addition of an OpenCL software development kit (SDK) allows system developers and programmers familiar with C to quickly and easily develop high-performance, low-power FPGA-based applications using an open, high-level programming language. The OpenCL SDK reduces hardware design complexity and enables C-skilled software programmers to work with FPGAs.
The enhancements to Altera's Qsys system integration tool and DSP Builder tool further improve system design productivity and performance. Qsys now offers enhanced support for the standard ARM® AXI3 and AXI4 protocols, while DSP Builder provides expanded support for seven floating-point precisions, including IEEE 754 half-precision, single-precision, and double-precision. To further simplify system design, the latest Quartus II software release includes a 100G Interlaken IP core for high-speed chip-to-chip packet transfers and a new IP core for video tracking, geared toward video processing applications.
Quartus II software version 12.1 is the first available within the new Partial Reconfiguration design workflow for Stratix® V FPGAs. Partial reconfiguration offers the flexibility to vary the core functionality of the device on the fly while other sections of the FPGA design remain operational. Designers store different functions in external memory and load them into the FPGA as needed, allowing customers to reduce the size of the FPGA used in their system, resulting in space and power savings. Quartus II software version 12.1 also includes other enhancements, including support for new devices. This version provides support for various FPGAs and FPGA-on-a-SoCs of the 28 nm Stratix V, Arria® V, and Cyclone® V, including full support for the Arria V GZ FPGA.
