Researchers at MIT and other centers have developed a decoding chip that uses a new statistical model to utilize this reliability information in a much simpler and faster way than conventional techniques.

The chip uses a universal decoding algorithm previously developed by the team, capable of deciphering any error-correcting code. Typically, decoding hardware can only process a specific type of code. This new universal decoder chip has broken the record for energy-efficient decoding, with performance 10 to 100 times greater than other hardware.

This advancement could enable mobile devices with fewer chips, as they would no longer require separate hardware for multiple codes. This would reduce the amount of material needed for manufacturing, lowering costs and improving sustainability. By making the decoding process less energy-intensive, the chip could also improve device performance and extend battery life. This could be especially useful for demanding applications such as augmented and virtual reality and 5G networks.

"This is the first time anyone has broken the 1 picojoule per bit decoding barrier. That's roughly the same amount of energy needed to transmit a bit within the system. It was a huge symbolic threshold, but it also shifts the balance at the receiver of what might be the most energy-intensive part: we can move it from the decoder to other elements," says Muriel Médard, NEC Professor of Software Science and Engineering at the Faculty of Science, lecturer in the Department of Electrical and Computer Engineering, and co-author of a paper introducing the new chip.

Médard's co-authors include lead author Arslan Riaz, a graduate student at Boston University (BU); Rabia Tugce Yazicigil, an assistant professor of electrical and computer engineering at BU; and Ken R. Duffy, then director of the Hamilton Institute at Maynooth University and now a professor at Northeastern University, as well as others from MIT, BU, and Maynooth University. The work is being presented at the International Conference on Solid State Circuits.

Smarter sorting

Digital data is transmitted over a network in the form of bits (0s and 1s). The sender encodes the data by adding an error-correcting code, which is a redundant string of 0s and 1s that can be considered a hash. Information about this hash is stored in a specific codebook. A decoding algorithm at the receiver, designed for this particular code, uses its codebook and the hash structure to recover the original information, which may have been scrambled by noise. Because each algorithm is specific to a code, and most require specific hardware, a device would need many chips to decode different codes.

The researchers had already demonstrated GRAND (Guessing Random Additive Noise Decoding), a universal decoding algorithm capable of breaking any code. GRAND works by guessing the noise that affected the transmission, subtracting that noise pattern from the received data, and then checking what remains against a codebook. It guesses a series of noise patterns in the order in which they are likely to occur.

Data is typically received with reliability information, also called soft information, which helps the decoder determine which fragments are errors. The new decoding chip, called ORBGRAND (Ordered Reliability Bits GRAND), uses this reliability information to classify the data based on the probability of each bit being an error.

But it's not as simple as ordering individual bits. While the least reliable bit might be the most likely to be an error, the third and fourth bits together might have the same probability of being an error as the seventh least reliable bit. ORBGRAND uses a new statistical model that can rank bits in this way, considering that several bits together have just as much probability of being an error as a few individual bits.

"If your car isn't working, basic information might tell you it's probably the battery. But if it's not just the battery, it might be the battery and the alternator together causing the problem. That's how a rational person would troubleshoot: they would say it could actually be these two things together before moving on to something that's much less likely," says Médard.

ORBGRAND stops sorting as soon as it finds a keyword, which usually happens very quickly. The chip also uses parallelization, generating and testing multiple noise patterns simultaneously to find the keyword faster. Because the decoder stops working once it finds the keyword, its power consumption remains low even when running multiple processes concurrently.

Record efficiency

When its method was compared to that of other chips, ORBGRAND decoded with maximum accuracy while consuming only 0.76 picojoules of energy per bit, breaking the previous performance record. ORBGRAND consumes between 10 and 100 times less energy than other devices.

One of the biggest challenges in developing the new chip was its low energy consumption, says Médard. With ORBGRAND, noise sequence generation is now so energy-efficient that other processes the researchers hadn't previously focused on, such as keyword checking in a codebook, consume most of the effort.

"Now, this testing process, which is like turning on the car to see if it works, is the hardest part. So we have to find more efficient ways to do it," he explains.

The team is also exploring ways to modify the modulation of the transmissions to take advantage of the ORBGRAND chip's increased efficiency. They also plan to study how to use their technique to more efficiently manage multiple overlapping transmissions.

The research is funded, in part, by the U.S. Defense Advanced Research Projects Agency (DARPA) and the Science Foundation of Ireland.

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Written by Adam Zewe, MIT News Office