Surface requirements vary depending on the high-performance chips and the smaller z-form factor of 3D integration. Cost-reduction strategies involve exploring alternative materials and improving manufacturing efficiency. In the field of 3D integration, microbump technology continues to advance to achieve smaller steps, with innovative Cu-Cu connection methods such as hybrid head bonding achieving steps of <1 micron. This article presents hybrid Cu-Cu technology, including its development, the high-level methodology for achieving it, and key applications. This article shares some of the research from the IDTechEx report "Advanced Semiconductor Packaging 2024-2034: Forecasts, Technologies, Applications.".

Introduction to microbump and hybrid bonding technology

Microbump technology, deeply rooted in semiconductor packaging, is based on the thermal compression bonding (TCB) process and has a wide range of applications in various products. Its evolution primarily revolves around the continuous scaling of the bumping step. However, a significant obstacle arises: reducing the size of the solder balls leads to increased formation of intermetallic compounds (IMCs), compromising conductivity and mechanical properties. Furthermore, the proximity of the contact gaps can cause bridging between solder balls during reflow, with the consequent risk of chip failure. Since solder and IMCs have higher resistivity than copper, their use in packaging high-performance components faces limitations.

On the other hand, hybrid junctions represent a paradigm shift by establishing interconnections through a combination of dielectric material (e.g., SiO2 or SiCN) and embedded metal (Cu). In particular, Cu-Cu hybrid junctions have achieved step sizes of less than 10 micrometers, typically in the single-digit µm range. This advancement offers several advantages, such as increased I/O, higher bandwidth, improved 3D vertical stacking, increased energy efficiency, and reduced parasitic interference and thermal resistance due to the absence of filler. However, this advanced technique still presents manufacturing challenges and high costs.

Three forms of hybrid Cu-Cu bonding

There are three main methods for achieving hybrid bonding: die-to-die (D2D), die-to-wafer (D2W), and wafer-to-wafer (W2W). Each method offers distinct advantages and disadvantages, which influence its suitability for various applications.

Die-to-die (D2D) bonding offers the highest assembly throughput, as both pellets can be individually tested before bonding. This method also offers the greatest design flexibility. However, its throughput is very low, and it presents significant difficulties during the process, particularly regarding edge effects, contamination, and particles introduced during singulation. Furthermore, pellet-to-pellet bonding requires exceptionally high-precision pick-and-place equipment. Due to these manufacturing difficulties and low throughput, this method currently has limited commercial use in hybrid bonding applications.

Wafer-to-wafer bonding is notable for its high throughput, which is crucial in the semiconductor industry. The process steps are simpler than in wafer-to-wafer bonding, as there is no need to cut the wafers or perform pick-and-place procedures. However, wafer-to-wafer bonding can reduce throughput and design flexibility, since the top and bottom wafers must be the same size. Despite these drawbacks, wafer-to-wafer bonding remains the most widely used method for bonding Cu-Cu hybrids in current commercial applications.

Tablet-to-wafer bonding occupies a middle ground between tablet-to-tablet and wafer-to-wafer bonding methods. This method offers greater design flexibility and performance than wafer-to-wafer bonding. However, it faces challenges related to lower yield and more complex processing requirements. Despite these difficulties, tablet-to-wafer bonding has gained traction due to its ability to strike a balance between design flexibility and manufacturing efficiency.

In general, the choice of hybrid junction method depends on factors such as assembly performance requirements, design flexibility, performance considerations, and processing challenges. Each method offers distinct advantages and disadvantages, which determine its applicability in semiconductor packaging and integration.

Hybrid Junction Applications in HPC Chips
The most prominent adoption of hybrid junction is by AMD, which employs TSMC's SOIC 3D (hybrid junction) technology to stack L3 cache chips on a single computing chip in two product lines: the AMD Ryzen 7000X3D consumer desktop CPUs (including AMD Ryzen™ 9 7950X3D and AMD Ryzen 7 5800X3D) and the EPYC processor for high-performance computing (HPC). AMD emphasizes the role of hybrid junction in exceeding its power efficiency goals with the chiplet-enabled and 3D architecture. They highlight its superiority over 3D microbump technology, citing 15 times greater interconnect density and 3 times greater power efficiency. Other examples include Graphcore's Bow Intelligence Processing Unit (BOW), the world's first 3D Wafer-on-Wafer (WoW) processor, which utilizes TSMC's 7nm technology and TSMC's 3D SoIC technology for a 3D array, with 1,472 IPU-Core tiles and 900MB of on-processor memory, delivering up to 40% faster AI performance and 16% higher performance per watt compared to its 2D predecessor. Another key example is the use of hybrid junction in high-bandwidth memory (HBM). Major players in the HBM market, such as SK Hynix, Samsung, and Micron, are increasingly exploring hybrid junction for their applications. While micropump stacking has been the traditional HBM method, the growing demand for higher bandwidth and energy efficiency is driving active research into hybrid junction. Hybrid-junction-based HBMs are expected to be commercialized in the next generation or later, offering a substantial competitive advantage over microbump-based alternatives. This will give these competitors a significant edge over the current market leader.

Summary

Hybrid bonding technology is poised to revolutionize the landscape of future HPC and AI products, offering a range of advantages that will shape the industry.

Author: Dr. Yu-Han Chang, Senior Technology Analyst at IDTechEx