These challenges increase as interconnect speeds increase. At 64 GT/s (gigatransfers per second), signal integrity limitations can restrict system scalability and overload server architectures. In response, Microchip Technology has introduced its XpressConnect™ PCIe® 6.0 and CXL® 3.1 retimers to facilitate memory expansion and resource disaggregation in large AI installations.
The timers are designed to extend the signal range beyond the conventional electrical limitations of PCIe Gen 5 and Gen 6, enabling more flexible system designs on complex motherboards, risers, and cable interconnects. These timers are engineered to meet these requirements through higher-bandwidth connectivity, all while adhering to the thermal and economic demands of modern AI installations. XpressConnect timers achieve pin-to-pin latency of less than 12 ns, approximately 80% lower than the PCIe 6.0 specification. This low latency helps to better utilize AI accelerators and GPUs by reducing data bottlenecks in high-density AI clusters.
“AI data centers are increasingly constrained not only by computing power, but also by the ability to efficiently move data throughout the system. With PCIe 6.0 pushing speeds up to 64 GT/s, signal range and latency become paramount,” said Brian McCarson, corporate vice president and general manager of Microchip’s data center solutions business unit. “Our XpressConnect timers are designed to function as a high-performance neural hub for the AI server, helping customers build more scalable and energy-efficient data centers by reducing latency and improving connectivity in dense GPU clusters.”
This system-level approach offers data center architects the ability to leverage underutilized resources and improve the overall efficiency of the platform.”.
The XpressConnect timers complete Microchip’s data center portfolio and are designed to work alongside the company’s 3nm Switchtec™ PCIe Gen 6 switches, Adaptec® SmartRAID controllers, Host Bus Adapters (HBAs), and Flashtec™ NVMe® controllers, helping to provide a pre-validated and interoperable architecture. Microchip’s XpressConnect PCIe Gen 6 and CXL 3.1 timers can be integrated with PCIe Gen 3, Gen 4, and Gen 5 platforms as needed, helping to accelerate time to market. These timers also connect to Microchip’s ChipLink diagnostic ecosystem, providing a unified graphical user interface for real-time 2D visual capture and four-level pulse amplitude modulation (PAM4) telemetry. These features enable data center operators to monitor link status more effectively and simplify troubleshooting, all of which helps reduce the total cost of ownership.
XpressConnect timers, designed as ready-to-use standard solutions, are intended to reduce the risk of vendor lock-in for hyperscalers. The devices also support flexible link branch configurations (1x16, 2x8, and 4x4) and adhere to widely adopted timer form factor guidelines, while providing enterprise-grade features such as hot-plugging and end-to-end data integrity. Visit the website for more information on Microchip's high-performance computing, storage, and connectivity solutions for data centers
Development Tools:
Microchip's ChipLink diagnostic tools offer comprehensive debugging, diagnostics, configuration, and analysis through an intuitive graphical user interface (GUI). ChipLink connects via in-band PCIe or sideband signals such as UART, TWI, and EJTAG, enabling flexible and efficient monitoring and troubleshooting throughout the design and deployment process.
