The ZL40292 (85Ω termination) and ZL40293 (100Ω termination) are specifically designed to meet the new DB2000Q specification, while the ZL40294 (85Ω termination) and ZL40295 (100Ω termination) are designed to meet the DB2000QL standard. These new devices also comply with PCIe Gen 1, 2, 3, and 4 specifications.
Each buffer is an ideal complement to circuit boards when distributed clocking is required across multiple peripheral components, such as central processing units (CPUs), field programmable gate arrays (FPGAs), and physical layers (PHYs) in data center servers and storage devices, as well as in many other PCIe applications. The low jitter added by these devices, approximately 20 femtoseconds (~20 fs), far surpasses the DB2000Q/QL specification of 80 femtoseconds (80 fs). This provides designers with ample headroom to meet tight deadlines and increase data throughput. These devices minimize jitter by distributing clocks across up to 20 outputs, thus preserving the integrity and quality of the clock signal throughout the buffer.
The new buffers achieve low power dissipation, thus reducing consumption thanks to LP-HCSL (Low-Power High-Speed Current Steering Logic). Compared to standard HCSL logic, LP-HCSL consumes one-third of the power, representing a significant reduction.
This feature also allows customers to run longer traces on the board, improving signal routing and reducing the number of components and board space. The ZL40292, for example, can eliminate up to 80 termination resistors (four per output) compared to traditional HCSL buffers.
The ZL40292 and ZL40293 are now available for sampling and volume production and are supplied in 72-pin, 10 x 10 mm QFN packages. The ZL40294 and ZL40295 are now available for sampling in 80-pin, 6 x 6 mm QFN packages.
