The new design, called Cinco Ranch, integrates multiple IPs developed within the Barcelona Zettascale Laboratory (BZL) in collaboration with Intel Foundry. Cinco Ranch will be manufactured on Intel 3, the most advanced technology node used to date by the Lizard series.
Key improvements over previous generations:
• New out-of-order dual-issue Lizard Ka core, integrated with the Vitruvius++ vector processing unit (VPU).
• Vitruvius++ supports the RISC-V v1.0 vector extension and is BSC's first 16-channel VPU, geared towards scientific applications.
• New out-of-order Lizard Ox core for high single-threaded performance.
• Third core based on the Sargantana processor design, optimized for energy efficiency.
• Three-level cache hierarchy with private L1 and L2 caches and a shared L3 cache.
• Industrial-grade SoC integrating BSC IPs and high-performance controllers provided by IFS, including DDR5 memory and PCIe Gen3 controllers, along with a high-frequency PLL.
Technical details of the Cinco Ranch processor:
• Lizard Ox: 11-stage scalar pipeline, 8-instruction issue, out-of-order, RV64IMAFDC ISA, privileged ISA 1.12.
• Lizard Ka: 11-stage scalar pipeline, dual issue, out-of-order, RV64IMAFDV ISA, privileged ISA 1.11.
• Vitruvius++: 16-channel decoupled vector accelerator with light out-of-order capabilities, RVV-1.0 extension, connected to Lizard Ka via Open Vector Interface (OVI).
• Sargantana: 7-stage in-order scalar pipeline, RV64IMAFD ISA, 128-bit integer SIMD extension, custom extensions for genomic applications.
• Internally developed L1 instruction cache and performance monitoring unit (PMU).
• High-performance L1 data cache (HPDS) from the OpenHW project.
• Private L2 and shared L3 caches based on OpenPiton.
• JTAG debug ring on Sargantana.
• Integrated PLL operating between 600 MHz and 2.8 GHz.
• 25 MHz RTC clock.
• PCIe Gen3 x8 with up to 8 GB/s bandwidth at 500 MHz.
• 16 GB DDR5 SODIMM memory, 4.8 GHz, 38.4 GB/s.
• Essential peripheral controllers: JTAG, UART, SPI, QSPI, OSPI, PWM, I2C, I3C, DMA, GPIO, thermal sensor, watchdog timer, 8 programmable timers, bootROM.
• 2 MB of scratchpad SRAM.
• Configurable fuses and straps.
• Intel-specific VISA debug signals.
• Power management unit.
• Technology node: Intel3.
• Area: 16 mm² (chip), 3.2 mm² (BSC IPs).
Cinco Ranch represents a key milestone within the Barcelona Zettascale Lab (BZL), a strategic initiative led by the BSC-CNS, with support from the Government of Spain and the European Union through the PERTE Chip program. The BZL aims to position Europe at the forefront of advanced chip design by developing high-performance RISC-V processors and integrating them into future European supercomputers.
This initiative drives innovation in hardware-software co-design, promotes sustainability, energy efficiency, and European technological sovereignty. It also reflects strong collaboration with industry leaders such as Intel and fosters inclusion, academic training, and industrial impact.
This project is co-financed by the Ministry for Digital Transformation and Public Administration, within the framework of the Recovery, Transformation and Resilience Plan, and supported
by the European Union – NextGenerationEU.
