The Switchtec Gen 6 family includes the first PCIe Gen 6 switches on the market manufactured using a 3nm process and is designed to reduce power consumption and support up to 160 lanes for high-density AI system connectivity. Advanced security features include a hardware root of trust and secure boot using secure post-quantum cryptography compliant with CNSA (Commercial National Security Algorithm Suite) 2.0.

Previous generations of PCIe created bandwidth bottlenecks as data was transferred between CPUs, GPUs, memory, and storage, resulting in underutilization and wasted compute cycles. PCIe 6.0 doubles the bandwidth of PCIe 5.0 to 64 GT/s (gigatransfers per second) per lane, providing the necessary channel to deliver data at all times to the most powerful AI accelerators. Switchtec Gen 6 PCIe switches enable high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators, and storage devices, and are designed to help data center architects unlock the full potential of next-generation AI and cloud infrastructure.

“The rapid pace of innovation in the AI ​​era is driving data center architectures away from traditional designs and toward a model where components are organized as a pool of shared resources,” said Brian McCarson, corporate vice president of Microchip’s data center solutions business unit. “By extending our well-known Switchtec product line to PCIe 6.0, we are facilitating this transformation with technology that enables direct communication between computing resources and delivers the most powerful and energy-efficient switch we have developed to date.”

Functioning as a high-performance interconnect, the switches provide simpler, more direct interfaces between GPUs in a server rack, which is crucial for reducing signal loss and maintaining the low latency required by AI. The PCIe 6.0 standard also includes a Flow Control Unit (FLIT) mode, a lightweight Forward Error Correction (FEC) system, and dynamic resource allocation.

These changes make data transfer more efficient and reliable, especially for the small packets that typically characterize AI workloads. The result is an overall increase in processing speed and lower effective latency.

Switchtec Gen 6 PCIe switches feature 20 ports and 10 stacks with controllers for hot-plugging and surprise plug-ins. Switchtec also supports Non-Transparent Bridging (NTB) for connecting and isolating multiple host domains and multicast for distributing data to multiple recipients within a single domain. The switch design incorporates advanced error containment along with diagnostic and debugging capabilities, numerous I/O interfaces, and an integrated MIPS processor with x8 and x16 branching options. The input and output reference clocks are based on PCIe stacks with four input clocks per stack. Visit the website for more information on Microchip's complete PCIe switch catalog.

Development Tools:
The Switchtec Gen 6 PCIe switch family is supported by Microchip's ChipLink diagnostic tools, which offer debugging, diagnostics, configuration, and analysis through an easy-to-use graphical user interface. ChipLink connects via in-band PCIe or sideband signals such as UART, TWI, and EJTAG, enabling efficient monitoring and troubleshooting throughout the design and deployment process. The switches are also supported by the PM61160-KIT evaluation kit for Switchtec Gen 6 PCIe switches, which is compatible with various interfaces.

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