“MIPS is bringing Physical AI to autonomous edge platforms that need modern AI capabilities in a scalable, highly efficient, open, and standards-based way. MIPS delivers increased performance and efficiency for our customers’ autonomous platforms with the MIPS S8200 RISC-V NPU,” said Sameer Wasson, CEO of MIPS. “MIPS’ virtual platform, Atlas Explorer, allows our customers to move quickly and begin optimizing models before silicon is even built. MIPS is enabling autonomous edge platforms that will bring AI from the data center to physical commercial and industrial products.”.
ForwardEdge ASIC, a wholly owned subsidiary of Lockheed Martin and a trusted provider of microelectronics solutions for critical applications in the aerospace, defense, and other high-reliability industries, has selected the MIPS S8200 for an upcoming high-performance ASIC intended for autonomous platforms.
“Our mission to build high-performance solutions for autonomous platforms requires leading performance and high area density when running the most advanced AI models,” said Frank Ferrante, CEO of ForwardEdge ASIC. “The MIPS S8200 delivers the superior performance and efficiency we need for our advanced mission-critical platforms.”.
The MIPS S8200 provides the multimodal intelligence needed to run Physical AI on autonomous edge platforms, including neural networks for vision, radar, voice, and more, along with sophisticated contextual awareness. MIPS's software-first approach allows customers to begin optimizing models on virtual platforms using MIPS Atlas Explorer. These core models enable the co-design of hardware and software, unlocking greater efficiencies and application optimizations. Combined with the open and modular standards of RISC-V, MIPS reduces platform development costs.
In 2027, MIPS expects to offer the first silicon reference platforms with the MIPS S8200 NPU to accelerate the adoption of Physical AI in autonomous edge devices. These evaluation platforms will showcase the performance and efficiency of MIPS AI platforms and drive the development of the ecosystem of tools to support the adoption of RISC-V—including Vector and Matrix extensions—in autonomous edge applications.
