The ARM® Development Studio 5 (DS-5™) Altera Edition toolkit is designed to eliminate the debugging barrier between the integrated dual-core CPU subsystem and the FPGA fabric in Altera SoC devices. By combining the most advanced multi-core debugger for the ARM architecture with the ability to adapt to the logic contained within the FPGA, the new toolkit provides embedded software developers with an unparalleled level of whole-chip visibility and control through the standard DS-5 user interface.
Altera's SoC devices combine a dual-core ARM Cortex-A9 processor and FPGA logic in a single device, giving users the power and flexibility to create application-programmable SoCs by implementing user-defined peripherals and hardware accelerators within the FPGA fabric. Altera is currently supplying initial samples of its Cyclone V SoC devices.
The ARM Development Studio 5 (DS-5) Altera Edition tool suite dynamically adapts to the FPGA configurations within the SoC for each customer, fully extending embedded debugging capabilities beyond the CPU-FPGA boundaries and unifying all software debugging information from the CPU and FPGA domains with the standard DS-5 user interface. When combined with the advanced multi-core debugging capabilities of the DS-5 debugger and connected to the Quartus II SignalTap logic analyzer for multi-shots, the toolset delivers an unparalleled level of debug visibility and control, resulting in a remarkable increase in productivity.
The ARM DS-5 tool suite offers the most advanced multi-core debugger on the market for the ARM architecture. It provides debugging capabilities for systems implementing asymmetric multiprocessing (AMP) and symmetric multiprocessing (SMP) configurations. It is frequently used for board generation, driver development, operating system portability, application development from scratch, and Linux debugging via JTAG and Ethernet interfaces, and offers real-time insights into Linux and operating systems.
Key Features and Benefits:
The Altera DS-5 ARM Toolset includes the following features:
• Its software debugging capabilities are tailored to include developer-programmed peripheral devices within the FPGA fabric, providing a comprehensive view of the peripheral register memory map in both hardware and software across the entire SoC.
• The DS-5 debugger simultaneously displays debug/scan data for Cortex-A9 processor cores and CoreSight™-compliant custom logic cores implemented within the FPGA fabric.
• The Altera Blaster JTAG USB debug cable is compatible with the DS-5 debugger and other Altera JTAG-based tools for the Altera SoC device.
• It enables the non-intrusive capture and display of signal events within the FPGA fabric that can be correlated over time with software events and processor instruction scans.
• It offers support for advanced hardware-level multi-triggering at the signal level between the CPU and FPGA logic domains, enabling code debugging across hardware/software domains.
• It includes the DS-5 Streamline performance analyzer, which maps software thread and event information to SoC and FPGA hardware counters, enabling the identification and correction of system-level bottlenecks.
